Equipe de recherche DART
For the last few years we have seen the beginning of the “design gap”. This gap is caused by the exponential growth of the integration rate of transistors on chips and the comparatively slower growth of the productivity of the integrated circuits designers. It is now impractical to fill a chip with custom designed logic. One has to reuse existing design parts or fill the chip area with memory (a good example of this evolution is the multi-core processors that include several existing processing cores instead of complexifying a single core). This evolution is clearly attested by the International Technology Roadmap on semiconductors.
In the same time, the computing power requirements of intensive signal processing applications such as video processing, voice recognition, telecommunications, radar or sonar are steadily increasing (several hundreds of Gops for low power embedded systems in a few years). New algorithms and new technologies introduce dynamic reconfiguration system on chip in the design flow. If the design productivity does not increase dramatically, the limiting factor of the growth of the semiconductor industry will not be the physical limitations due to the thinness of the fabrication process but the economy! Indeed we ask to the system design teams to build more complex systems faster, cheaper, bug free and decreasing the power consumption...
We propose in the DaRT project to contribute to the improvement of the productivity of the electronic embedded system design teams. We structure our approach around a few key ideas:
Promote the use of parallelism to help reduce the power consumption while improving the performance.
Use of MDE(Model Driven Engineering) by separating the concerns in different models allowing reuse of these models and to keep them human readable.
Propose an environment starting at the highest level of abstraction, namely the system modeling level.
Automate code production by the use of (semi)-automatic model transformations to build correct by construction code.
Develop simulation techniques at precise abstraction levels (functional, transactional or register transfer levels) to check the design the soonest.
Prototype the resulting embedded systems of FPGA and dynamically reconfigurable FPGA.
Promote strong semantics in the application model to allow verification, non ambiguous design and automatic code generation.
Focus on a limited application domain, intensive signal processing applications. This restriction allows us to push our developments further without having to deal with the wide variety of applications.
All these ideas are implemented into a prototype co-design environment based on a model driven engineering approach, Gaspard. This open source platform is our test bench and is freely available. To help the designer, such an environment should help to evaluate several architectural solutions as well as several application specifications with regard to their performance and cost. We are able to estimate metrics from SystemC simulations and the refactoring algorithm defined for the transformation of loops to particular multiprocessors are the first steps for exploration. Automatic exploration system based on multi-objective methods has to transform the SoC description (size, network, memory, association). The space of solutions is huge and a fast simulation in SystemC at a high abstraction level is a good opportunity to reduce the space in a short delay. After that, a precise simulation at low level in SystemC or even in VHDL (synthetizable VHDL) can start to refine the solution. Code production is also focussed for GPGPU using OpenCL language as an intermediary target.
The main technologies we promote are UML 2 and MARTE profil, MDE and Eclipse EMF for the modeling and model handling; Array-OL , , , and synchronous languages as computation models with strong semantics for verification; SystemC for the simulation; OpenMP for the shared memory parallel execution; OpenCL for the massively parallel GPU;VHDL for the synthesis; and Java to code our prototypes.
est arrêtée depuis le 31/12/2011
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