Equipe de recherche AOSTE
Embedded System Design
Typical embedded software applications display a mix of multimedia signal/data processing with modal interfaces, resulting in heterogenous concurrent data-flow streaming models, and often stringent real-time constraints. Similarly, embedded architectural platforms are becoming increasingly parallel, with dedicated hardware accelators and manycore processors. The optimized compilation of such kinds of applications onto such execution platforms involves complex mapping issues, both in terms of spatial distribution and in terms of temporal scheduling. Currently, it is far from being a fully automatic compilation process as in the case of commodity PC applications. Models are thus needed, both as formal mathematical objects from theoretical computer science to provide foundations for embedded system design, and also as engineering models to support an effective design flow.
Our general approach is directly inspired from the theories of synchronous languages, process networks, and of real-time distributed scheduling. We insist on the introduction of logical time as functional design ingredient to be explicitly considered as first-class modeling element of systems. Logical time is based on logical clocks, where such a clock can be defined as any meaningful sequence of event occurrences, usually meant as activation/triggering conditions for actions and operations in the systems. So logical time can be multiform, a global partial order built from local total orders of clocks. In the course of the design flow time refinement takes place, as decison are made towards placement and timing of various tasks and operations. This solves in part the constraints between clocks, committing to schedule and placement decisions. The final version should be totally ordered, and then subjet to physical timing verification as to physical constraints.
The general (logical) Time Model has been standardized as part of the OMG profile for Modeling and Analysis of Real-Time Embedded systems (MARTE).
Work on polychronous formalisms (descending from Esterel), on a Clock Constraint Specification Language (CCSL) handling logical time, on Application-Architecture Adequation approach and real-time scheduling results has been progressed over the years, resulting in sofware environments such as SynDEx or TimeSquare.
est arrêtée depuis le 31/12/2016
En savoir plus
Retrouvez sur le site web RAweb
- le rapport d'activité complet de l'équipe AOSTE (en anglais)
- le rapport d'activité de toutes nos équipes de recherche (en anglais)
- Rapport d'activité complet 2016
- Rapport d'activité complet 2015
- Rapport d'activité complet 2014
- Rapport d'activité complet 2013
- Rapport d'activité complet 2012
- Rapport d'activité complet 2011
- Rapport d'activité complet 2010
- Rapport d'activité complet 2009
- Rapport d'activité complet 2008
- Rapport d'activité complet 2007
- Rapport d'activité complet 2006
- Rapport d'activité complet 2005
- Rapport d'activité complet 2004