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COSI Research team

Codesign of Silicon Systems

  • Leader : Sanjay Rajopadhye
  • Research center(s) : CRI Rennes - Bretagne Atlantique
  • Field : Networks and systems
  • Theme : Architectures and Systems

Team presentation

The project COSI works on methods and tools for implementing complete systems on silicon.

The challenges for designing such systems are:

  • an evolving palette of target technologies (full custom VLSI, reconfigurable components (FPGA), and hybrid hardware software, often with the software running on special purpose instruction set processors (ASIPs));
  • fast time-to-market (and hence rapid design);
  • a increasing complexity of the systems being designed.

Research themes

COSI emphasizes on three themes, completed by the implementation of real applications and studies on algorithmics.

  • Synthesis of dedicated systems from high level specifications. COSI leans on research carried out on the Alpha language and its development environment, MMAlpha. MMAlpha allows Alpha programs to be handled with the goal to generate, either regular architectures from high-level specifications, or code pour programmable architectures.
  • ASIPs design. It is a question of producing, for a particular application, at the same time the architecture and the compiler allowing performances required by the application to be achieved. The techniques are based on a modeling of the architecture of the target processor, and on the flexible compilation environment Calife, under development.
  • Reconfigurable Computing. The goal of developed tools concerns the automatic implementation regular architectures on reconfigurable platforms.
  • Applications: image and signal processing, telecommunication, high performance computing, molecular biology, fundamental algorithms.

International and industrial relations

  • Collaboration with Indian Statistical Institute, Calcutta on Compilation and Optimization for Reconfigurable CO-processors, funded by a grant from CEFIPRA.

  • Collaboration with the university of Trois Rivières, Québec. Filtering architectures are studied and synthesized in order to be implemented on reconfigurable circuits or integrated circuits, funded by a grant from AUF.
  • Contract with Cnet and France-Télécom R&D for hardware-software co-design for ATM applications.

Keywords: Parallel architecture Systolic architecture Vlsi Asic Cad/cam Architecture simulation Architecture synthesis Genome Video signal processing