- HAL publications
CASH Research team
Compilation and Analysis, Software and Hardware
- Leader : Matthieu Moy
- Type : team
- Research center(s) : Grenoble
- Field : Algorithmics, Programming, Software and Architecture
- Theme : Architecture, Languages and Compilation
- Inria teams are typically groups of researchers working on the definition of a common project, and objectives, with the goal to arrive at the creation of a project-team. Such project-teams may include other partners (universities or research institutions)
The advent of parallelism in supercomputers and in more classical end-user computers increases the need for high-level code optimization and improved compilers. The need for power-efficient computing have motivated the raise of various kinds of accelerators like GPU and more recently many-cores and FPGA in data-center. Writing efficient applications for these heterogeneous systems requires new approaches for software, compilers and runtimes.
Parallelism based on dataflow is one way to address this issue. A dataflow application is made of several actors that can perform computations and communicate with other actors. It can be implemented in several ways: as software running on a parallel general-purpose architecture or on accelerators like GPU or many-core, or as hardware implementation, possibly running on reconfigurable chips (FPGA).
The overall objective of the CASH team is to take advantage of the characteristics of the specific hardware (generic hardware, hardware accelerators or FPGA) to compile energy efficient software and hardware. The long-term objective is to provide solutions for the end-user developers to use at their best the huge opportunities of these emerging platforms.
- Dataflow models for HPC applications: We target representations that are expressive enough to express all kinds of parallelism and allow further optimizations.
- Compiler algorithms and tools for irregular applications: The extensions of these intermediate representations to enable complex control flow and complex data structures, and the design of associated analysis for optimized code generation for multicore processors and accelerators.
- Compiler Algorithms, Simulation and Tools for Reconfigurable Circuits: The application of the two preceding activities on High Level Synthesis, with additional resource constraints.
- Simulation of Systems on a Chip: A parallel and scalable simulation of Systems-on-Chips, which, combined with the preceding activity, will result in a complete workflow for circuit design.