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CAIRN Research team
Energy Efficient Computing ArchItectures with Embedded Reconfigurable Resources
- Leader : Olivier Sentieys
- Type : Project team
- Research center(s) : Rennes
- Field : Algorithmics, Programming, Software and Architecture
- Theme : Architecture and Compiling
- Ecole normale supérieure de Cachan, Université Rennes 1, CNRS, Institut de recherche en informatique et systèmes aléatoires (IRISA) (UMR6074)
Team presentation
The scientific aim of the CAIRN team is to study reconfigurable system-on-chip, i.e. hardware systems whose configuration may change before or even during execution. To this end, CAIRN intends to approach reconfigurable architectures from three angles: the invention of new reconfigurable platforms, the development of associated transformation, compilation and synthesis tools, and the exploration of the interaction between algorithms and architectures.
Reconfigurable systems have been considered by research and industry for some years thanks to possibilities opened up initially by Field Programmable Gate Arrays (FPGA) technology and more recently by reconfigurable processors.
Recent evolutions in technology and modern hardware systems confirm that reconfigurable systems are increasingly used in recent applications or embedded into more general system-on-chip. Rapidly changing application standards in fields such as communications and information security ask for frequent modifications of the devices. Hardware reconfiguration can adapt the system to changing conditions. Moreover, this adaptation of a flexible hardware to the application software leads to significant gain in terms of performance and energy efficiency.
However, reconfigurable systems raise several challenges like the architecture structure itself, its dynamic reconfiguration capabilities or the associated compilation/synthesis methods and tools.
Research themes
Design of dynamically reconfigurable or domain-specific architectures with focus on dynamic behavior, reconfiguration management and energy efficiency
Architecture description language for reconfigurable architectures
Reconfigurable system management
Reconfigurable memory structure
Flexible arithmetic operators
Multimode components
Development of associated compilation and transformation techniques
Pattern-based compilation and configuration synthesis for reconfigurable platform
Synthesis of nested loop accelerator from C specification
Floating-point to fixed-point transformations
Multi-mode IP synthesis
Resource or energy constrained optimization of signal processing algorithms
Fixed Point accuracy analytical evaluation
Precoding schemes for 4G/MIMO systems
Cooperative MIMO for sensor networks
High-rate true random number generation
Application domains are mobile communications, wireless sensor networks, network security and video processing.
International and industrial relations
Members of CAIRN team are involved in several national or international projects:
- ITEA2 - GEODES: Global Energy Optimisation for Distributed Embedded Systems (2008-2011)
- Nano2012 S2S4HLS Source-to-Source Transformations for High-Level Synthesis
- Nano2012 RECMOTIFS Pattern Recognition for Automatic Generation of Specialized Accelerators for Multimedia Applications
- ANR Architectures du Futur - CIFAER: Flexible Intra-Vehicule Communications and Embedded Reconfigurable Architectures (2008-2011)
- ANR Architectures du Futur - FOSFOR: Flexible Operating System FOr Reconfigurable platform (2008-2011)
- Pôle Images et Réseaux - SPRING: Shelf Proof Random Integrated Number Generator (2008-2009)
- Pôle Images et Réseaux - Transmedia: Video transcoding on reconfigurable platforms (2008-2010)
- ANR Technologies Logicielles SoCLib: An Open Modeling and Simulation Platform for System-on-Chip Design (2007-2010), http://soclib.lip6.fr
- ANR Architectures du Futur - ROMA: Reconfigurable Operators for Multimedia Applications (2007-2010), http://roma.irisa.fr/
- ANR Telecom SVP: SurVeiller et Prévenir (2006-2008), http://svp.irisa.fr/
- ANR Actions de Recherche Amont SSIA - OverSoc (2005-2008), http://oversoc.ensea.fr/
- ANR Multimedia Semim@ge (2007-2010)
- PEPS CNRS with ENS Cachan/SATIE on energy scavenging and power software management in the human environment
- PEPS CNRS FiltrOptim with ENS Lyon/LIP on Efficient and robust signal processing: optimization of digital filter synthesis in fixed-point and floating-point arithmetic
- Fastnet: Fast Adaptative Secure Technology for high-speed NETwork (2005-2008)
- CAPTIV: Consommation et strAtégies cooPératives pour les Transmissions entre Infrastructure et Véhicules (2006-2008), http://captiv.irisa.fr/
The CAIRN team has currently some collaboration with the following laboratories, universities or research institutes:
- INRIA project-teams: Pops, Swing, Arenaire, Espresso, Symbiose, TexMex
- SATIE (ENS Cachan), LEAT Nice, Lab-Sticc (Lorient, Brest), ETIS Cergy, LIP6 Paris, IETR Rennes, Ireena Nantes, Telecom Bretagne Brest
- CEA List, CEA Leti
- CNRS GDR SOC-SIP (System On Chip - System In Package) and GDR ISIS (Information Signal ImageS), GdR ASR (Architecture Système Réseau)
- INRIA associated team with Laval University (Québec, Canada): ASTER
- CoMap project with University of Erlangen-Nuremberg and TU Dresden (Germany)
- IMEC (Belgium), Colorado state U. (USA), University of Québec (Trois-Rivères, Canada), Lund U. (Sweden), U. Girona (Spain), UC Riverside (USA), University College Cork (Ireland), University of Massachusetts (USA), University of Adelaide (Australia), University of Colorado State, Fort-Collins (USA), Los Alamos National Laboratory (USA), University of Queensland (Australia)
- U. of Yaoundé (Cameroon), U. of Tunis (Tunisia), ENPA (Algeria)
Members of CAIRN team have collaboration with large companies or SMEs like STmicroelectronics, Thomson, Alcatel-Lucent, Orange Labs, Thales, Atmel, Xilinx, Phillips, Infineon, Envivio, Geensys, Aphycare Technologies, SmartQuantum, R-interface, Sensaris, Ditocom, Sestream, Eca-Faros.
Keywords: Embedded systems System-on-chip Reconfigurable architectures Specialized accelerators High-level synthesis Loop parallelization Flexible compilation Low-power consumption Fixed-point arithmeti
Research teams of the same theme :
Contact
Team leader
Olivier Sentieys
(See all teams)
Tel.: +33 2 96 46 90 41
Secretariat
Tel.: +33 2 99 84 22 09
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See also